A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor


A distributed critical-path timing monitor (CPM) is designed as part of the POWER6trade microprocessor in 65nm SOI. The CPM is capable of monitoring timing margin, process variation, localized noise and V<sub>DD</sub> droop, or clock stability. It tracks critical-path delay to within 3 FO2 delays at extreme operating voltages with a standard deviation less than frac12 an FO2 delay. The CPM detects DC V<sub>DD</sub> droops greater than 10mV and tracks timing changes greater than 1 FO2 delay.


1 Figures and Tables

Download Full PDF Version (Non-Commercial Use)